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Longer digital trace further from analog vs shorter digital trace closer to analog

How serial resistors actually reduce EMI?VCC trace routing on a two-layer board with TQFP chipPCB routing: EMI and signal integrity, return current questionsPower origin and power planes placement on PCB50MHz SPI PCB routing, use vias or resistors?PCB layout: am I doing local power nets correctly?PCB layout for SOIC packaged op ampOptimize signal return path with decoupling capacitors in a two layer boardMulti-layer layout and return currents of high-speed signalsReal current return pathAsynchronous SRAM routing crosstalk concerns

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1

$begingroup$

In the 4 layer PCB below (top layer) what is better in terms of interference with the analog circuitry on the lower left (current sense amp and buffer op-amp) trace 1 or 2?

The FPGA does have bypass capacitors on the bottom side.
The stackup that I'm currently planning to use is 0.8 mm/4 layer (0.035-0.2-0.0175-0.265-0.0175-0.2-0.035)

The traces are from an ADC to an FPGA, the clock frequency is 50MHz.
My understanding is that having ground and power planes underneath the traces would make the high frequency component of the signals return under the traces.
So placing the traces further away from the analog seems like it might reduce the interference, on the other hand a longer trace is a bigger loop area.

pcb-design high-speed

share|improve this question

asked 9 hours ago

axkaxk

41844 silver badges1616 bronze badges

$endgroup$

• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  keep them far apart
  $endgroup$
  – analogsystemsrf
  8 hours ago
  

  
  
  
  


• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  @analogsystemsrf, you mean #1 on the screenshot?
  $endgroup$
  – axk
  8 hours ago
  

  
  
  
  


• 
  
  
  

  
  1
  

  
  
  
  
  
  

  
  $begingroup$
  If you add a series termination resistor near the driver then that should help regardless of whether you use approach #1 or #2.
  $endgroup$
  – Mr. Snrub
  7 hours ago
  

  
  
  
  

add a comment | 

1

$begingroup$

In the 4 layer PCB below (top layer) what is better in terms of interference with the analog circuitry on the lower left (current sense amp and buffer op-amp) trace 1 or 2?

The FPGA does have bypass capacitors on the bottom side.
The stackup that I'm currently planning to use is 0.8 mm/4 layer (0.035-0.2-0.0175-0.265-0.0175-0.2-0.035)

The traces are from an ADC to an FPGA, the clock frequency is 50MHz.
My understanding is that having ground and power planes underneath the traces would make the high frequency component of the signals return under the traces.
So placing the traces further away from the analog seems like it might reduce the interference, on the other hand a longer trace is a bigger loop area.

pcb-design high-speed

share|improve this question

asked 9 hours ago

axkaxk

41844 silver badges1616 bronze badges

$endgroup$

• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  keep them far apart
  $endgroup$
  – analogsystemsrf
  8 hours ago
  

  
  
  
  


• 
  
  
  

  
  

  
  
  
  
  
  

  
  $begingroup$
  @analogsystemsrf, you mean #1 on the screenshot?
  $endgroup$
  – axk
  8 hours ago
  

  
  
  
  


• 
  
  
  

  
  1
  

  
  
  
  
  
  

  
  $begingroup$
  If you add a series termination resistor near the driver then that should help regardless of whether you use approach #1 or #2.
  $endgroup$
  – Mr. Snrub
  7 hours ago
  

  
  
  
  

add a comment | 

$begingroup$

In the 4 layer PCB below (top layer) what is better in terms of interference with the analog circuitry on the lower left (current sense amp and buffer op-amp) trace 1 or 2?

The FPGA does have bypass capacitors on the bottom side.
The stackup that I'm currently planning to use is 0.8 mm/4 layer (0.035-0.2-0.0175-0.265-0.0175-0.2-0.035)

The traces are from an ADC to an FPGA, the clock frequency is 50MHz.
My understanding is that having ground and power planes underneath the traces would make the high frequency component of the signals return under the traces.
So placing the traces further away from the analog seems like it might reduce the interference, on the other hand a longer trace is a bigger loop area.

pcb-design high-speed

share|improve this question

asked 9 hours ago

axkaxk

41844 silver badges1616 bronze badges

$endgroup$

share|improve this question

asked 9 hours ago

axkaxk

41844 silver badges1616 bronze badges

share|improve this question

asked 9 hours ago

axkaxk

41844 silver badges1616 bronze badges

asked 9 hours ago

axkaxk

41844 silver badges1616 bronze badges

asked 9 hours ago

axkaxk

41844 silver badges1616 bronze badges

3 Answers
3

active

oldest

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2

$begingroup$

placing the traces further away from the analog seems like it might
reduce the interference, on the other hand a longer trace is a bigger
loop area

You have not shown the power and ground plane. I assume it to be solid underneath the traces as I don't see any other components or via in the region.

• If there are no more traces to be drawn, go for the one with the least trace length. If hte matching is well done, the interference will be really less.


• There will be no big loop area even if you go for lengthier trace. Almost all the high-speed currents will be just below the trace. Only disadvantage is that the signal is close to the edge which might be susceptible to external noise.

share|improve this answer

answered 8 hours ago

UmarUmar

5,18633 gold badges1212 silver badges3636 bronze badges

$endgroup$

add a comment | 

1

$begingroup$

Coupling field strength generally falls off at distance squared. If you can make the parasitic loop length increase by less than distance squared (e.g. not a big circle, but linear), then, first order, moving the undesired coupling loop farther away is likely to be a win.

share|improve this answer

answered 8 hours ago

hotpaw2hotpaw2

1,56522 gold badges2020 silver badges3030 bronze badges

$endgroup$

add a comment | 

0

$begingroup$

The return current does spread out on the ground plane beneath the trace, so keeping the traces apart reduces how much of the return currents from both traces overlap each other on the ground plane.

share|improve this answer

answered 7 hours ago

DKNguyenDKNguyen

6,62311 gold badge77 silver badges2828 bronze badges

$endgroup$

add a comment | 

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2

$begingroup$

placing the traces further away from the analog seems like it might
reduce the interference, on the other hand a longer trace is a bigger
loop area

You have not shown the power and ground plane. I assume it to be solid underneath the traces as I don't see any other components or via in the region.

• If there are no more traces to be drawn, go for the one with the least trace length. If hte matching is well done, the interference will be really less.


• There will be no big loop area even if you go for lengthier trace. Almost all the high-speed currents will be just below the trace. Only disadvantage is that the signal is close to the edge which might be susceptible to external noise.

share|improve this answer

answered 8 hours ago

UmarUmar

5,18633 gold badges1212 silver badges3636 bronze badges

$endgroup$

add a comment | 

2

$begingroup$

placing the traces further away from the analog seems like it might
reduce the interference, on the other hand a longer trace is a bigger
loop area

You have not shown the power and ground plane. I assume it to be solid underneath the traces as I don't see any other components or via in the region.

• If there are no more traces to be drawn, go for the one with the least trace length. If hte matching is well done, the interference will be really less.


• There will be no big loop area even if you go for lengthier trace. Almost all the high-speed currents will be just below the trace. Only disadvantage is that the signal is close to the edge which might be susceptible to external noise.

share|improve this answer

answered 8 hours ago

UmarUmar

5,18633 gold badges1212 silver badges3636 bronze badges

$endgroup$

add a comment | 

$begingroup$

placing the traces further away from the analog seems like it might
reduce the interference, on the other hand a longer trace is a bigger
loop area

You have not shown the power and ground plane. I assume it to be solid underneath the traces as I don't see any other components or via in the region.

• If there are no more traces to be drawn, go for the one with the least trace length. If hte matching is well done, the interference will be really less.


• There will be no big loop area even if you go for lengthier trace. Almost all the high-speed currents will be just below the trace. Only disadvantage is that the signal is close to the edge which might be susceptible to external noise.

share|improve this answer

answered 8 hours ago

UmarUmar

5,18633 gold badges1212 silver badges3636 bronze badges

$endgroup$

share|improve this answer

answered 8 hours ago

UmarUmar

5,18633 gold badges1212 silver badges3636 bronze badges

answered 8 hours ago

UmarUmar

5,18633 gold badges1212 silver badges3636 bronze badges

answered 8 hours ago

UmarUmar

5,18633 gold badges1212 silver badges3636 bronze badges

1

$begingroup$

Coupling field strength generally falls off at distance squared. If you can make the parasitic loop length increase by less than distance squared (e.g. not a big circle, but linear), then, first order, moving the undesired coupling loop farther away is likely to be a win.

share|improve this answer

answered 8 hours ago

hotpaw2hotpaw2

1,56522 gold badges2020 silver badges3030 bronze badges

$endgroup$

add a comment | 

1

$begingroup$

Coupling field strength generally falls off at distance squared. If you can make the parasitic loop length increase by less than distance squared (e.g. not a big circle, but linear), then, first order, moving the undesired coupling loop farther away is likely to be a win.

share|improve this answer

answered 8 hours ago

hotpaw2hotpaw2

1,56522 gold badges2020 silver badges3030 bronze badges

$endgroup$

add a comment | 

$begingroup$

Coupling field strength generally falls off at distance squared. If you can make the parasitic loop length increase by less than distance squared (e.g. not a big circle, but linear), then, first order, moving the undesired coupling loop farther away is likely to be a win.

share|improve this answer

answered 8 hours ago

hotpaw2hotpaw2

1,56522 gold badges2020 silver badges3030 bronze badges

$endgroup$

share|improve this answer

answered 8 hours ago

hotpaw2hotpaw2

1,56522 gold badges2020 silver badges3030 bronze badges

answered 8 hours ago

hotpaw2hotpaw2

1,56522 gold badges2020 silver badges3030 bronze badges

answered 8 hours ago

hotpaw2hotpaw2

1,56522 gold badges2020 silver badges3030 bronze badges

0

$begingroup$

The return current does spread out on the ground plane beneath the trace, so keeping the traces apart reduces how much of the return currents from both traces overlap each other on the ground plane.

share|improve this answer

answered 7 hours ago

DKNguyenDKNguyen

6,62311 gold badge77 silver badges2828 bronze badges

$endgroup$

add a comment | 

0

$begingroup$

The return current does spread out on the ground plane beneath the trace, so keeping the traces apart reduces how much of the return currents from both traces overlap each other on the ground plane.

share|improve this answer

answered 7 hours ago

DKNguyenDKNguyen

6,62311 gold badge77 silver badges2828 bronze badges

$endgroup$

add a comment | 

$begingroup$

The return current does spread out on the ground plane beneath the trace, so keeping the traces apart reduces how much of the return currents from both traces overlap each other on the ground plane.

share|improve this answer

answered 7 hours ago

DKNguyenDKNguyen

6,62311 gold badge77 silver badges2828 bronze badges

$endgroup$

share|improve this answer

answered 7 hours ago

DKNguyenDKNguyen

6,62311 gold badge77 silver badges2828 bronze badges

answered 7 hours ago

DKNguyenDKNguyen

6,62311 gold badge77 silver badges2828 bronze badges

answered 7 hours ago

DKNguyenDKNguyen

6,62311 gold badge77 silver badges2828 bronze badges