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Memory capability and powers of 2
How does a RAM work with a CPU?How to calculate index and tag fields lengths for a cpu cache?Differences, uses, and theory of volatile and nonvolatile memory?Determining memory address width from memory sizeWhat is the type of memory of a USB Flash drive and on a hard disc?Page table - I don't understand how this table has been madeIs it possible, and if so, how difficult would it be, to replace the volatile memory in Gameboy games with non-volatile memory?How does triple level cell FLASH memory achieve 3 bits per cell?Difference between a memory cell and a memory chip?Memory dump size does not match size of MTD partitionMaximum cells in a row in a SRAM memory array
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Why are computer memory capabilities often multiples of a power of two, such as 2^10 = 1024 bytes?
I think it is something related to the binary logic, but I do not understand the precise reason for that.
memory computers binary non-volatile-memory flash-memories
asked 9 hours ago
Kinka-ByoKinka-Byo
3782 silver badges7 bronze badges
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add a comment |
$begingroup$
Why are computer memory capabilities often multiples of a power of two, such as 2^10 = 1024 bytes?
I think it is something related to the binary logic, but I do not understand the precise reason for that.
memory computers binary non-volatile-memory flash-memories
asked 9 hours ago
Kinka-ByoKinka-Byo
3782 silver badges7 bronze badges
$endgroup$
add a comment |
$begingroup$
Why are computer memory capabilities often multiples of a power of two, such as 2^10 = 1024 bytes?
I think it is something related to the binary logic, but I do not understand the precise reason for that.
memory computers binary non-volatile-memory flash-memories
asked 9 hours ago
Kinka-ByoKinka-Byo
3782 silver badges7 bronze badges
$endgroup$
Why are computer memory capabilities often multiples of a power of two, such as 2^10 = 1024 bytes?
I think it is something related to the binary logic, but I do not understand the precise reason for that.
memory computers binary non-volatile-memory flash-memories
memory computers binary non-volatile-memory flash-memories
asked 9 hours ago
Kinka-ByoKinka-Byo
3782 silver badges7 bronze badges
asked 9 hours ago
Kinka-ByoKinka-Byo
3782 silver badges7 bronze badges
edited 9 hours ago
Kinka-Byo
asked 9 hours ago
Kinka-ByoKinka-Byo
3782 silver badges7 bronze badges
asked 9 hours ago
Kinka-ByoKinka-Byo
3782 silver badges7 bronze badges
asked 9 hours ago
Kinka-ByoKinka-Byo
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3 Answers
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Memory addresses are binary numbers. The range of an N-bit (unsigned) binary number is 0 to 2N-1, a total of 2N different values.
Since addresses are passed to memory chips as binary numbers, it makes sense to build them in capacities of powers of 2. That way, none of the address space is wasted, and it's easy to combine multiple chips/modules to build larger memory systems with no gaps in the address space.
answered 9 hours ago
Dave Tweed♦Dave Tweed
131k10 gold badges164 silver badges282 bronze badges
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A 1024 x 1 memory chip requires 10 address lines and you get full utilisation of all addresses. Now, if someone brought out a 600 x 1 memory chip, it would still need 10 address lines. It can’t use 9 because that could only uniquely define 512 memory positions.
Then think of what would happen if someone wanted to use two of the 600 x 1 memory chips to give a combined memory size of 1200. How would the address lines (plus 1 more) cope with numerically embracing each address slot uniquely and, if there is an MCU incrementing through memory in order to store contiguous data, that MCU would need special knowledge about the binary address numbers that are unused.
answered 8 hours ago
Andy akaAndy aka
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With 1 address wire you can access 2 different addresses. With N address bits or wires, you can access 2^N different addresses. Not much more complex than labeling 10 different items with single decimal digit or 26 different items with a single letter (depending on how many letters you have in your alphabet of course).
answered 6 hours ago
JustmeJustme
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3 Answers
3
active
oldest
votes
3 Answers
3
active
oldest
votes
active
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active
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$begingroup$
Memory addresses are binary numbers. The range of an N-bit (unsigned) binary number is 0 to 2N-1, a total of 2N different values.
Since addresses are passed to memory chips as binary numbers, it makes sense to build them in capacities of powers of 2. That way, none of the address space is wasted, and it's easy to combine multiple chips/modules to build larger memory systems with no gaps in the address space.
answered 9 hours ago
Dave Tweed♦Dave Tweed
131k10 gold badges164 silver badges282 bronze badges
$endgroup$
add a comment |
$begingroup$
Memory addresses are binary numbers. The range of an N-bit (unsigned) binary number is 0 to 2N-1, a total of 2N different values.
Since addresses are passed to memory chips as binary numbers, it makes sense to build them in capacities of powers of 2. That way, none of the address space is wasted, and it's easy to combine multiple chips/modules to build larger memory systems with no gaps in the address space.
answered 9 hours ago
Dave Tweed♦Dave Tweed
131k10 gold badges164 silver badges282 bronze badges
$endgroup$
add a comment |
$begingroup$
Memory addresses are binary numbers. The range of an N-bit (unsigned) binary number is 0 to 2N-1, a total of 2N different values.
Since addresses are passed to memory chips as binary numbers, it makes sense to build them in capacities of powers of 2. That way, none of the address space is wasted, and it's easy to combine multiple chips/modules to build larger memory systems with no gaps in the address space.
answered 9 hours ago
Dave Tweed♦Dave Tweed
131k10 gold badges164 silver badges282 bronze badges
$endgroup$
Memory addresses are binary numbers. The range of an N-bit (unsigned) binary number is 0 to 2N-1, a total of 2N different values.
Since addresses are passed to memory chips as binary numbers, it makes sense to build them in capacities of powers of 2. That way, none of the address space is wasted, and it's easy to combine multiple chips/modules to build larger memory systems with no gaps in the address space.
answered 9 hours ago
Dave Tweed♦Dave Tweed
131k10 gold badges164 silver badges282 bronze badges
answered 9 hours ago
Dave Tweed♦Dave Tweed
131k10 gold badges164 silver badges282 bronze badges
answered 9 hours ago
Dave Tweed♦Dave Tweed
131k10 gold badges164 silver badges282 bronze badges
answered 9 hours ago
Dave Tweed♦Dave Tweed
131k10 gold badges164 silver badges282 bronze badges
131k10 gold badges164 silver badges282 bronze badges
add a comment |
add a comment |
$begingroup$
A 1024 x 1 memory chip requires 10 address lines and you get full utilisation of all addresses. Now, if someone brought out a 600 x 1 memory chip, it would still need 10 address lines. It can’t use 9 because that could only uniquely define 512 memory positions.
Then think of what would happen if someone wanted to use two of the 600 x 1 memory chips to give a combined memory size of 1200. How would the address lines (plus 1 more) cope with numerically embracing each address slot uniquely and, if there is an MCU incrementing through memory in order to store contiguous data, that MCU would need special knowledge about the binary address numbers that are unused.
answered 8 hours ago
Andy akaAndy aka
250k11 gold badges193 silver badges445 bronze badges
$endgroup$
add a comment |
$begingroup$
A 1024 x 1 memory chip requires 10 address lines and you get full utilisation of all addresses. Now, if someone brought out a 600 x 1 memory chip, it would still need 10 address lines. It can’t use 9 because that could only uniquely define 512 memory positions.
Then think of what would happen if someone wanted to use two of the 600 x 1 memory chips to give a combined memory size of 1200. How would the address lines (plus 1 more) cope with numerically embracing each address slot uniquely and, if there is an MCU incrementing through memory in order to store contiguous data, that MCU would need special knowledge about the binary address numbers that are unused.
answered 8 hours ago
Andy akaAndy aka
250k11 gold badges193 silver badges445 bronze badges
$endgroup$
add a comment |
$begingroup$
A 1024 x 1 memory chip requires 10 address lines and you get full utilisation of all addresses. Now, if someone brought out a 600 x 1 memory chip, it would still need 10 address lines. It can’t use 9 because that could only uniquely define 512 memory positions.
Then think of what would happen if someone wanted to use two of the 600 x 1 memory chips to give a combined memory size of 1200. How would the address lines (plus 1 more) cope with numerically embracing each address slot uniquely and, if there is an MCU incrementing through memory in order to store contiguous data, that MCU would need special knowledge about the binary address numbers that are unused.
answered 8 hours ago
Andy akaAndy aka
250k11 gold badges193 silver badges445 bronze badges
$endgroup$
A 1024 x 1 memory chip requires 10 address lines and you get full utilisation of all addresses. Now, if someone brought out a 600 x 1 memory chip, it would still need 10 address lines. It can’t use 9 because that could only uniquely define 512 memory positions.
Then think of what would happen if someone wanted to use two of the 600 x 1 memory chips to give a combined memory size of 1200. How would the address lines (plus 1 more) cope with numerically embracing each address slot uniquely and, if there is an MCU incrementing through memory in order to store contiguous data, that MCU would need special knowledge about the binary address numbers that are unused.
answered 8 hours ago
Andy akaAndy aka
250k11 gold badges193 silver badges445 bronze badges
answered 8 hours ago
Andy akaAndy aka
250k11 gold badges193 silver badges445 bronze badges
answered 8 hours ago
Andy akaAndy aka
250k11 gold badges193 silver badges445 bronze badges
answered 8 hours ago
Andy akaAndy aka
250k11 gold badges193 silver badges445 bronze badges
250k11 gold badges193 silver badges445 bronze badges
add a comment |
add a comment |
$begingroup$
With 1 address wire you can access 2 different addresses. With N address bits or wires, you can access 2^N different addresses. Not much more complex than labeling 10 different items with single decimal digit or 26 different items with a single letter (depending on how many letters you have in your alphabet of course).
answered 6 hours ago
JustmeJustme
5,4862 gold badges6 silver badges17 bronze badges
$endgroup$
add a comment |
$begingroup$
With 1 address wire you can access 2 different addresses. With N address bits or wires, you can access 2^N different addresses. Not much more complex than labeling 10 different items with single decimal digit or 26 different items with a single letter (depending on how many letters you have in your alphabet of course).
answered 6 hours ago
JustmeJustme
5,4862 gold badges6 silver badges17 bronze badges
$endgroup$
add a comment |
$begingroup$
With 1 address wire you can access 2 different addresses. With N address bits or wires, you can access 2^N different addresses. Not much more complex than labeling 10 different items with single decimal digit or 26 different items with a single letter (depending on how many letters you have in your alphabet of course).
answered 6 hours ago
JustmeJustme
5,4862 gold badges6 silver badges17 bronze badges
$endgroup$
With 1 address wire you can access 2 different addresses. With N address bits or wires, you can access 2^N different addresses. Not much more complex than labeling 10 different items with single decimal digit or 26 different items with a single letter (depending on how many letters you have in your alphabet of course).
answered 6 hours ago
JustmeJustme
5,4862 gold badges6 silver badges17 bronze badges
answered 6 hours ago
JustmeJustme
5,4862 gold badges6 silver badges17 bronze badges
answered 6 hours ago
JustmeJustme
5,4862 gold badges6 silver badges17 bronze badges
answered 6 hours ago
JustmeJustme
5,4862 gold badges6 silver badges17 bronze badges
5,4862 gold badges6 silver badges17 bronze badges
add a comment |
add a comment |
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